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QPRO XQR4000XL Radiation Hardened FPGAs
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Product Specification * Systems-oriented features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12 mA sink current per output Configured by loading binary file - Unlimited reprogrammability Readback capability - Program verification - Internal node observability Development system runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization Highest capacity: over 130,000 usable gates Buffered interconnect for maximum speed New latch capability in configurable logic blocks Improved VersaRingTM I/O interconnect for better fixed pinout flexibility - Virtually unlimited number of clock signals Optional multiplexer or 2-input function generator on device outputs 5V tolerant I/Os Advanced 0.35 process Processed on Xilinx QML line
XQR4000XL Series Features
* * * * * * * Radiation-hardened FPGAs for space and satellite applications Guaranteed total ionizing dose Latch-up immune Low soft upset rate Guaranteed to meet full electrical specifications over -55C to +125C Available in -3 speed System featured FPGAs - SelectRAMTM memory: on-chip ultra-fast RAM with * synchronous write option * dual-port RAM option - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - Eight global low-skew clock or signal distribution networks System performance beyond 60 MHz Flexible array architecture Low power segmented routing architecture
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Table 1: XQR4000XL Series Radiation Hardened Field Programmable Gate Arrays Max. Logic Gates (No RAM) 13,000 36,000 62,000 Max. RAM Bits (No Logic) 18,432 41,472 73,728 Typical Gate Range (Logic and RAM)(1) 10,000 - 30,000 22,000 - 65,000 40,000 - 130,000 Number of Flip-Flops 1,536 3,168 5,376 Max. User I/O 192 288 384
Device XQR4013XL XQR4036XL XQR4062XL
Logic Cells 1,368 3,078 5,472
CLB Matrix 24 x 24 36 x 36 48 x 48
Total CLBs 576 1,296 2,304
Packages CB228 CB228 CB228
Notes: 1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
(c) 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Radiation Specifications
Symbol TID SEL SEU SEU SEU SEU SEU Total ionizing dose Single event Latch-up LET> 100 MeV Single event upset galactic p+(1) Single event upset galactic heavy Ion(1) Single event upset trapped Single event upset galactic p+(1) p+(2) CM2/mg. @ +125C Description Min Max 60K 0 2.43E - 8 9.54E - 8 2.50E - 7 5.62E - 8 2.43E - 7 Upsets/ Bit-Day Upsets/ Bit-Day Upsets/ Bit-Day Upsets/ Bit-Day Single event upset galactic heavy Ion(2) Upsets/ Bit-Day
Notes: 1. 680 Km LEO, 98o Inclination, 100-mil Al Shielding 2. 35,000 Km GEO, 0o Inclination, 100-mil Al Shielding 3. Simulations done using Space Radiation Version 2.5 code from Severn Communication Corp.
Units RAD(Si)
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XQR4000XL Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Preliminary: Unmarked: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or devicefamilies. Values are subject to change. Use as estimates, not for production. Based on preliminary characterization. Further changes are not expected. Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. All specifications subject to change without notice.
Additional Specifications
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. For design considerations requiring more detailed timing information, see the appropriate family AC supplements available on the Xilinx web site at: http://www.xilinx.com/partinfo/databook.htm.
Absolute Maximum Ratings(1)
Symbol VCC VIN VTS VCCt TSTG TSOL TJ Supply voltage relative to GND Input voltage relative to GND(2) output(2) Voltage applied to High-Z Description -0.5 to 4.0 -0.5 to 5.5 -0.5 to 5.5 50 -65 to +150 +260 +150 Units V V V ms C C C
Longest supply voltage rise time from 1V to 3V Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Junction temperature
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Maximum DC overshoot or undershoot above VCC or below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to VCC + 2.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
Recommended Operating Conditions(1)
Symbol VCC VIH VIL TIN Description Supply voltage relative to GND, TC = -55C to +125C High-level input voltage(2) Low-level input voltage Input signal transition time Min 3.0 50% of VCC 0 Max 3.6 5.5 30% of VCC 250 Units V V V ns
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. 2. Input and output measurement threshold is ~50% of VCC.
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XQR4000XL DC Characteristics Over Recommended Operating Conditions
Symbol VOH VOL VDR ICCO IL CIN IRPU IRPD IRLL Description High-level output voltage at IOH = -4 mA, VCC min (LVTTL) High-level output voltage at IOH = -500 A, (LVCMOS) Low-level output voltage at IOL = 12 mA, VCC min Low-level output voltage at IOL = 1500 A, (LVCMOS) Quiescent FPGA supply current(2) Input or output leakage current Input capacitance (sample tested) Pad pull-up (when selected) at VIN = 0V (sample tested) Pad pull-down (when selected) at VIN = 3.6V (sample tested) Horizontal longline pull-up (when selected) at logic Low (LVTTL)(1) Min 2.4 90% VCC 2.5 -10 0.02 0.02 0.3 Max 0.4 10% VCC 5 +10 10 0.25 0.15 2.0 Units V V V V V mA A pF mA mA mA
Data retention supply voltage (below which configuration data may be lost)
Notes: 1. With up to 64 pins simultaneously sinking 12 mA. 2. With no output current loads, no active input or Longline pull-up resistors, all I/O pins in a High-Z state and floating.
Power-On Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current capacity to insure proper initialization, and the power supply ramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. The slowest ramp-up time is 50 ms. Current capacity is not specified for a ramp-up time faster than 2 ms. The current capacity varies linealy with ramp-up time, e.g., an XQR4036XL with a ramp-up time of 25 ms would require a capacity predicted by the point on the straight line drawn from 1A at 120 s to 500 mA at 50 ms at the 25 ms time mark. This point is approximately 750 mA .
Ramp-up Time Product XQR4013 - 36XL XC4062XL Description Minimum required current supply Minimum required current supply Fast (120 s) 1A 2A Slow (50 ms) 500 mA 500 mA
Notes: 1. Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may result in a larger initialization current. 2. This specification applies to Commercial and Industrial grade products only. 3. Ramp-up Time is measured from 0VDC to 3.6VDC. Peak current required lasts less than 3 ms, and occurs near the internal power on reset threshold voltage. After initialization and before configuration, ICC max is less than 10 mA.
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XQR4000XL AC Switching Characteristic
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature)
Global Buffer Switching Characteristics
-3 Symbol TGLS Description Delay from pad through Global Low Skew buffer, to any clock K Device XQR4013XL XQR4036XL XQR4062XL Min 0.6 1.1 1.4 Max 3.6 4.8 6.3 Units ns ns ns
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics
-3 Symbol TGE Description Delay from pad through Global Early buffer, to any IOB clock. Values are for BUFGEs 1, 2, 5 and 6. Device XQR4013XL XQR4036XL XQR4062XL Min 0.4 0.3 0.3 Max 2.4 3.1 4.9 Units ns ns ns
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics
-3 Symbol TGE Description Delay from pad through Global Early buffer, to any IOB clock. Values are for BUFGEs 3, 4, 7 and 8. Device XQR4013XL XQR4036XL XQR4062XL Min 0.7 0.9 1.2 Max 2.4 4.7 5.9 Units ns ns ns
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XQR4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQR4000XL devices and expressed in nanoseconds unless otherwise noted.
CLB Switching Characteristics
-3 Symbol
Combinatorial Delays
Description F/G inputs to X/Y outputs F/G inputs via H' to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via SR/H0 via H to X/Y outputs C inputs via H1 via H to X/Y outputs C inputs via DIN/H2 via H to X/Y outputs C inputs via EC, DIN/H2 to YQ, XQ output (bypass) Operand inputs (F1, F2, G1, G4) to C OUT Add/subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Carry net delay, C OUT to C IN Clock K to flip-flop outputs Q Clock K to latch outputs Q F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H
Min 1.1 2.2 2.0 1.9 2.0 0.9 1.0 0.6 2.3 3.4
Max 1.6 2.7 2.9 2.5 2.4 2.5 1.5 2.7 3.3 2.0 2.8 0.26 0.32 2.1 2.1 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TILO TIHO TITO THH0O THH1O THH2O TCBYP TOPCY TASCY TINCY TSUM TBYP TNET TCKO TCKLO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK
CLB Fast Carry Logic
Sequential Delays
Setup Time Before Clock K
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CLB Switching Characteristics (Continued)
-3 Symbol
Hold Time After Clock K
Description F/G inputs F/G inputs via H C inputs via SR/H0 through H C inputs via H1 through H C inputs via DIN/H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Clock High time Clock Low time Width (High)
Min 0 0 0 0 0 0 0 0 3.0 3.0 3.0 -
Max 3.7 19.8
Units ns ns ns ns ns ns ns ns ns ns ns ns ns
TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR
Clock
TCH TCL TRPW
Set/Reset Direct
Delay from C inputs via S/R, going High to Q TRIO Global Set/Reset TMRW Minimum GSR pulse width TMRQ FTOG Delay from GSR input to any Q Toggle frequency (MHz) (for export control)
See page 16 for TRRI values per device. 166 MHz
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XQR4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQR4000XL devices and are expressed in nanoseconds unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3 Symbol
Write Operation
Single Port RAM Address write cycle time (clock K period)
Size 16x2 32x1
Min 9.0 9.0 4.5 4.5 2.2 2.2 0 0 2.0 2.5 0 0 2.0 1.8 0 0 4.5 6.5 1.1 2.2
Max 6.8 8.1 1.6 2.7 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS
Clock K pulse width (active edge)
16x2 32x1
Address setup time before clock K
16x2 32x1
Address hold time after clock K
16x2 32x1
DIN setup time before clock K DIN hold time after clock K WE setup time before clock K
16x2 32x1 16x2 32x1 16x2 32x1
WE hold time after clock K
16x2 32x1
Data valid after clock K
16x2 32x1
Read Operation
TRC TRCT TILO TIHO TICK TIHCK
Address read cycle time
16x2 32x1
Data valid after address change (no Write Enable)
16x2 32x1
Address setup time before clock K
16x2 32x1
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Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3 Symbol
Write Operation
Dual Port RAM Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K
Size 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1
Min 9.0 4.5 2.5 0 2.5 0 1.8 0 -
Max
Units ns
TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS
7.8
ns ns ns ns ns ns ns ns
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XQR4000XL CLB Single-Port RAM Synchronous (Edge-Triggered) Write Timing
TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TAHS TDHS TWHS
TILO DATA OUT
TILO TWOS
OLD NEW
DS029_01_011300
XQR4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing
TWPDS WCLK (K) TWSS WE TDSDS DATA IN TASDS ADDRESS TAHDS TDHDS TWHS
TILO DATA OUT
TILO TWODS
OLD NEW
DS029_02_011300
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QPRO XQR4000XL Radiation Hardened FPGAs
XQR4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Output Flip-Flop, Clock to Out(1,2,3)
-3 Symbol TICKOF Description Global low skew clock to output using OFF(4) Device XQR4013XL XQR4036XL XQR4062XL TSLOW For output SLOW option add All Devices Min 1.5 2.0 2.3 3.0 Max 8.6 9.8 11.3 3.0 Units ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode configurations. 3. Output timing is measured at ~50% V CC threshold with 50 pF external capacitive load. 4. OFF = Output Flip-Flop
Output Flip-Flop, Clock to Out, BUFGEs 1, 2, 5, and 6
-3 Symbol TICKEOF Description Global early clock to output using OFF Values are for BUFGEs 1, 2, 5, and 6. Device XQR4013XL XQR4036XL XQR4062XL Min 1.3 1.2 1.2 Max 7.4 8.1 9.9 Units ns ns ns
Notes: 1. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter TOKPOF and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode configurations. 2. Output timing is measured at ~50% V CC threshold with 50 pF external capacitive load.
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Output Flip-Flop, Clock to Out, BUFGEs 3, 4, 7, and 8
-3 Symbol TICKEOF Description Global early clock to output using OFF Values are for BUFGEs 3, 4, 7, and 8. Device XQR4013XL XQR4036XL XQR4062XL Min 1.8 1.8 2.0 Max 8.8 9.7 10.9 Units ns ns ns
Notes: 1. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter TOKPOF and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode configurations. 2. Output timing is measured at ~50% V CC threshold with 50 pF external capacitive load.
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than 50 pF. For example, if the actual load capacitance is 120 pF, add 2.5 ns to the specified delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specified output delay. Figure 1 is usable over the specified operating conditions of voltage and temperature and is independent of the output slew rate control.
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2 Delta Delay (ns)
1
0
-1
-2 0 20 40 60 80 100 120 140
Capacitance (pF)
DS029_03_011300
Figure 1: Delay Factor at Various Capacitive Loads
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QPRO XQR4000XL Radiation Hardened FPGAs
XQR4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Global Low Skew Clock, Input Setup and Hold Times(1,2)
-3 Symbol
No Delay
Description Global early clock and IFF(3) Global early clock and FCL(4)
Device(1) XQR4013XL XQR4036XL XQR4062XL
Min 1.2 / 3.2 1.2 / 5.5 1.2 / 7.0 6.1 / 0.0 6.4 / 1.0 6.7 / 1.2 6.4 / 0.0 6.6 / 0.0 6.8 / 0.0
Units ns ns ns ns ns ns ns ns ns
TPSN/TPHN
Partial Delay
TPSP/TPHP
Global early clock and IFF(3) Global early clock and FCL(4)
XQR4013XL XQR4036XL XQR4062XL
Full Delay
TPSD/TPHD
Global early clock and IFF(3)
XQR4013XL XQR4036XL XQR4062XL
Notes: 1. The XQR4013XL, XQR4036XL, and XQR4062XL have significantly faster partial and full delay setup times than other devices. 2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification. 3. IFF = Input Flip-Flop or Latch 4. FCL = Fast Capture Latch
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Global Early Clock BUFEs 1, 2, 5, and 6 Setup and Hold for IFF and FCL(1,2)
-3 Symbol
No Delay
Description Global early clock and IFF(3) Global early clock and FCL(4)
Device XQR4013XL XQR4036XL XQR4062XL
Min 1.2 / 4.7 1.2 / 6.7 1.2 / 8.4 6.4 / 0.0 7.0 / 0.8 9.0 / 0.8 12.0 / 0.0 13.8 / 0.0 13.1 / 0.0
TPSEN/TPHEN TPFSEN/TPFHEN
Partial Delay
TPSEPN/TPHEP TPFSEP/TPFHEP
Full Delay
Global early clock and IFF(3) Global early clock and FCL(4)
XQR4013XL XQR4036XL XQR4062XL
TPSEPD/TPHED
Global early clock and IFF(3)
XQR4013XL XQR4036XL XQR4062XL
Notes: 1. The XQR4013XL, XQR4036XL, and XQR4062XL have significantly faster partial and full delay setup times than other devices. 2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification. 3. IFF = Input Flip-Flop or Latch 4. FCL = Fast Capture Latch
Global Early Clock BUFEs 3, 4, 7, and 8 Setup and Hold for IFF and FCL(1,2)
-3 Symbol
No Delay
Description Global early clock and IFF(3) Global early clock and FCL(4)
Device XQR4013XL XQR4036XL XQR4062XL
Min 1.2 / 4.7 1.2 / 6.7 1.2 / 8.4 5.4 / 0.0 6.4 / 0.8 8.4 / 1.5 10.0 / 0.0 12.2 / 0.0 13.1 / 0.0
TPSEN/TPHEN TPFSEN/TPFHEN
Partial Delay
TPSEPN/TPHEP TPFSEP/TPFHEP
Full Delay
Global early clock and IFF(3) Global early clock and FCL(4)
XQR4013XL XQR4036XL XQR4062XL
TPSEPD/TPHED
Global early clock and IFF(3)
XQR4013XL XQR4036XL XQR4062XL
Notes: 1. The XQR4013XL, XQR4036XL, and XQR4062XL have significantly faster partial and full delay setup times than other devices. 2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification. 3. IFF = Input Flip-Flop or Latch 4. FCL = Fast Capture Latch
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QPRO XQR4000XL Radiation Hardened FPGAs
XQR4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). -3 Symbol
Clocks
Description Clock enable (EC) to clock (IK) Delay from FCL enable (OK) active edge to IFF clock (IK) active edge Pad to clock (IK), no delay Pad to clock (IK), via transparent fast capture latch, no delay Pad to fast capture latch enable (OK), no delay All Hold Times
Device All devices All devices
Min 0.1 2.2
Max -
Units ns ns
TECIK TOKIK
Setup Times
TPICK TPICKF TPOCK
All devices All devices All devices All devices All devices XQR4013XL XQR4036XL XQR4062XL
1.7 2.3 1.2 0 -
19.8 15.9 22.5 29.1 1.6 3.1 3.7 1.7 1.8 3.6
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Hold Times
Global Set/Reset
TMRW TRRI
Minimum GSR pulse width Delay from GSR input to any Q(2)
Propagation Delays
TPID TPLI TPFLI TIKRI TIKLI TOKLI
Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent FCL and input latch, no delay Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) FCL enable (OK) active edge to I1, I2 (via transparent standard input latch)
All devices All devices All devices All devices All devices All devices
Notes: 1. IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch 2. Indicates Minimum Amount of Time to Assure Valid Data.
DS071 (v1.1) June 25, 2000 Product Specification
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QPRO XQR4000XL Radiation Hardened FPGAs
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XQR4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values are expressed in nanoseconds unless otherwise noted. -3 Symbol
Clocks
Description Clock High Clock Low Clock (OK) to pad Output (O) to pad High-Z to pad High-Z (slew-rate independent) High-Z to pad active and valid Output (O) to pad via fast output MUX Select (OK) to pad via fast MUX Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup time Clock Enable (EC) to clock (OK) hold time Minimum GSR pulse width Delay from GSR input to any XQR4013XL XQR4036XL XQR4062XL pad(2)
Min 3.0 3.0 0.5 0 0 0.3 19.8
Max 5.0 4.1 4.4 4.1 5.5 5.1 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns
TCH TCL TOKPOF TOPF TTSHZ TTSONF TOFPF TOKFPF TOOK TOKO TECOK TOKEC TMRW TRPO
Propagation Delays
Setup and Hold Times
Global Set/Reset
-
20.5 27.1 33.7 3.0
ns ns ns ns
Slew Rate Adjustment
TSLOW
For output SLOW option add
Notes: 1. Output timing is measured at ~50% V CC threshold, with 50 pF external capacitive loads. 2. Indicates Minimum Amount of Time to Assure Valid Data.
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DS071 (v1.1) June 25, 2000 Product Specification
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QPRO XQR4000XL Radiation Hardened FPGAs CB228 Package for XQR4013XL/4036XL/4062XL Pin Name CB228 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 IO IO_FCKL2 GND IO IO IO IO IO IO IO IO IO IO IO BUFGS_BL_GCK2_IO M1 GND M0 VCC M2 BUFGP_BL_GCK3_IO HDC_IO IO IO IO LDC_IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO
Pinouts
CB228 Package for XQR4013XL/4036XL/4062XL Pin Name GND BUFGP_TL_A16_GCK1_IO A17_IO IO IO TDI_IO TCK_IO IO IO IO IO IO IO GND IO_FCLK1 IO TMS_IO IO IO IO IO IO IO IO IO IO GND VCC IO IO IO IO IO IO IO IO VCC IO IO CB228 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39
DS071 (v1.1) June 25, 2000 Product Specification
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QPRO XQR4000XL Radiation Hardened FPGAs CB228 Package for XQR4013XL/4036XL/4062XL Pin Name IO IO IO IO /ERR_INIT_IO VCC GND IO IO IO IO IO IO IO IO VCC IO IO IO IO GND IO IO IO IO IO IO IO IO IO IO IO BUFGS_BR_GCK4_IO GND DONE VCC /PROG D7_IO BUFGP_BR_GCK5_IO IO CB228 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 CB228 Package for XQR4013XL/4036XL/4062XL Pin Name IO IO IO D6_IO IO IO IO IO IO GND IO IO IO IO D5_IO /CS0_IO IO IO IO IO D4_IO IO VCC GND D3_IO /RS_IO IO IO IO IO D2_IO IO VCC IO IO IO IO GND IO IO CB228 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159
R
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DS071 (v1.1) June 25, 2000 Product Specification
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QPRO XQR4000XL Radiation Hardened FPGAs CB228 Package for XQR4013XL/4036XL/4062XL Pin Name GND VCC A8_IO A9_IO A19_IO A18_IO IO IO A10_IO A11_IO VCC IO IO IO IO GND IO IO IO IO A12_IO A13_IO IO IO IO IO A14_IO BUFGS_TL_GCK8_A15_IO VCC CB228 P200 P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 P223 P224 P225 P226 P227 P228
CB228 Package for XQR4013XL/4036XL/4062XL Pin Name IO IO IO IO D1_IO BUSY_/RDY_RCLK_IO IO IO D0_DIN_IO BUFGS_TR_GCK6_DOUT_IO CCLK VCC TDO GND A0_/WS_IO BUFGP_TR_GCK7_A1_IO IO IO CSI_A2_IO A3_IO IO IO IO IO IO IO GND IO IO IO IO VCC A4_IO A5_IO IO IO A21_IO A20_IO A6_IO A7_IO CB228 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199
DS071 (v1.1) June 25, 2000 Product Specification
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QPRO XQR4000XL Radiation Hardened FPGAs
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Ordering Information
XQR 4062XL -3 CB 228 M
QPRO Radiation Hardened Temperature Range M = Military Ceramic (TC = -55C to +125C)
Device Type XQR4062XL XQR4036XL XQR4013XL Speed Grade
Number of Pins Package Type CB = Top Brazed Ceramic Quad Flat Pack
Revision History
The following table shows the revision history for this document Date 10/05/98 06/25/00 Version 1.0 1.1 Original document release. Updated format, added DS071 number. Updated timing specifications to match with commercial data sheet. Description
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DS071 (v1.1) June 25, 2000 Product Specification

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